During a chip design cycle, it is important to verify the behavior of the most critical signal paths at an earlier design stage in order to understand and identify possible problems and finding solutions thereof, which will be used at subsequent tuning steps to meet the design requirements and specification. For example, a clock signal controlling the data transfer within the system is such a critical signal. In the clock routing design, the most important criteria which directly affect the entire chip performance is a clock skew, i.e., the maximum difference in the signal arrival time at two different components over all clock destinations. Since a clock period (or clock cycle) must allow for logical completion of the task as well as extra time for deviations in clock arrival time among functional elements, the smaller amount of the maximum deviation in the clock arrival time allows the use of faster clocks. Thus, controlling the clock skew is the key to improve circuit performance.
In a complete circuit design, the input clock excitation signals are typically applied at particular locations according to the real on-chip clock source connections. Ideally, the clock signal is distributed in such a way that the interconnections carrying the clock signal to functional sub-blocks are equal in length. FIG. 1 schematically illustrates an example of a complete grid-based clock distribution network for a high performance processor design. As shown in FIG. 1, the clock distribution network design is based on a special purpose clock grid 10. The clock grid 10 is driven by a pregrid 12 which has a tree structure. The major purpose of the clock grid 10 is to deliver the clock signal to each and every destination with a minimum skew. Typically, a circuit design has a hierarchical structure, and, in a bottom-up design flow, circuit designs for smaller blocks are getting completed first. In FIG. 1, four blocks 1–4 are shown, and some of the completed metal layers 14 are illustrated for the block 4. As shown in FIG. 1, the completed clock design figures (clock signal lines) are connected to the clock grid 10 at specific locations, i.e., clock hook-ups 16.
FIG. 2 schematically illustrates a typical process for the block-level clock skew verification for a complete design. As shown in FIG. 2, the locations for clock grid hook-ups are identified based on the real grid geometry, and the corresponding ports are assigned (20). Voltage sources are then connected to the block-level netlist ports according to the identified clock grid hook-ups (22). Circuit simulation for the block-level netlist is run using a simulation program such as SPICE (24), and clock delays/skews at clock receivers such as functional elements are reported (26).
FIG. 3 schematically illustrates a typical process for the full-chip clock skew verification for a complete design. As shown in FIG. 3, the locations for clock grid hook-ups from each block are identified and the corresponding ports are assigned (30). Then circuit extraction is run for the full chip without blocks (inside-block information) to create a detailed netlist for the full chip (32). Extraction is also run for the blocks to create a netlist for each block (34). Typically, circuit extraction identifies the individual transistors and their interconnections on various layers, as well as the parasitic resistances and capacitances that are present between these layers. The extracted netlist provides a very accurate estimation of the actual device dimensions and device parasitics that determine the circuit performance. The extracted netlist file and parameters are subsequently used for verification process and post layout simulations. The extracted netlist for each block is replaced with a reduced order model which is computed for each grid hook-up port (36). Circuit simulation for the full-chip netlist is run using a simulation program such as SPICE (38), and then clock skew verification is run for each block (40).
However, in incomplete circuit design, some of such locations may be missing or physically disconnected. For example, the blocks 1, 2, 3, . . . may be prepared by different persons independently, and it may be necessary to verify clock skew distribution at a particular stage. However, some of the blocks may not have real grid connections yet and thus such a clock skew verification may not be available at the early stage.